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Analog3

What’s this project?

This is a software-controlled analog synthesizer project.

I believe the advantage of an analog synthesizer is smoothness of its “voice”.  Sound from VCO is so smooth and beautiful (I don’t know why though).

However, it has significant disadvantage when you want complex control of the sound.  For example, envelope generator gives so simple shape that outcome sound is sometimes “boring” especially with fast-attack onset.

Digital/software control does much better for such complex control.  So Analog3 will have analog sound modules that can be controlled by software.

Data Link and Transport Layers

Start Bit

Sender: Just set dominant to data bus.

Receiver: Start data read procedure.  Synchronize clock if necessary.

Wire ID

Sender: Send Wire ID.  Read every bit from the bus.  If one or more bits are different from sent one, this sender would back off.

Receiver: Read the wire ID from the bus.

Back Off Policy

If sender finds no conflict in the wire ID transfer, the sender proceeds to continue bit.  If the sender finds conflict, sender back off.

Receiver stops reading if continue bit is recessive.  Next coming dominant bit should be start bit for another frame.

Message Format

Overview

The picture below shows the layout of a message frame on the bus.

message_frame

A message frame consists of following parts:

message_frame {
start_bit : 1,
wire_id : 8,
continue_bit : 1,
data_length : 3,
data[data_length + 1] {
data : 8
},
stop_bit : 1
}

 Start Bit

Start bit notifies transferring a frame begins.  Always one dominant bit.  The receiver must start receiving the frame.

Wire ID

Wire ID is represented by 8 bit integer, MSB first.  A wire ID identifies transfer channel of data in the bus.  This ID may also used for conflict resolution.  Sender must also read wire ID from the bus.  If there is a conflict, read ID would be different from sent ID.  In such a case, sender must not continue and start over the transfer later.

Continue Bit

The sender should continue the frame if no conflict was found in the wire ID.  Sender must set dominant to continue bit to proceed.  This bit would be recessive if all senders back off for conflict, so receiver must stop reading the frame and start over for another frame.

Data Length

Three bit integer, MSB first.  Number of data bytes is data length plus 1.  So possible number of data bytes is from 1 to 8.

Data Bytes

8 bit integer, MSB first, repeating data_length + 1 times.

Stop Bit

Always recessive.  Maybe replaced by some simple CRC.

Goal/Requirements

  • The communication line should be usable as a patch wire.
  • The line should be usable also as a common data bus.
  • There should be no dedicated master.
  • Adapter has to be inexpensive.
  • Module plugin and disconnect should able to do online anytime.

Inter Module Communication Bus

Analog synth has a very simple control language which is voltage.  Any message is translated to voltage that can be universally read by any modules. So for example, VCO output is basically audio output but also can be used as control voltage of some other modules, such as VCO cross modulation.

This simple data exchange methodology makes analog synthesizer very versatile and flexible.  However, as a drawback, patch wiring would become too complicated as you make complex module network.

One solution for simplifying the wiring is to use a single common data bus where all modules are connected, and exchange data selectively using some software.  Apparently, making such a bus for analog signals is impossible or extremely difficult. So I’m going to try making it using a digital bus.

Bus Driver

I use dominant – recessive strategy for physical layer so that I can utilize CAN transceivers in market.

ver.1

The first version of bus driver was for proof of concept, so it was built as simple as possible by using Arduino units as follows.  One Arduino unit acts as a communication node.

phase1

Each unit connects to the data bus at digital pins 7 and 8.  Pin 7 is used for listener (input) and pint 8 is used for driver (output).  All OSI layers above physical is implemented by software.  The maximum achieved bit rate with this version was 10kbps.

ver.2

The second version of bus driver is for accelerating the bit rate.  CAN transceiver is used for the physical layer.  Data link and transport layers are still implemented by software but a dedicated processor is assigned for the task.

bus_driver_2nd

The driver exchanges data with the master module (is Arduino in this case) via SPI/USI.